Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a duty detection circuit and a duty cycle correction circuit including the same.
In semiconductor devices such as semiconductor memory devices designed to operate based on clocks, it is desirable to control a duty cycle of a clock. The 50% duty cycle of the clock means that a “high level duration” and a “low level duration” of a clock signal are equal to each other.
The semiconductor memory device may input/output data in synchronization with rising and falling edges of the clock. In such semiconductor devices, if the duty cycle of the clock is not 50%, data may not be inputted/outputted at the precise timing. Therefore, the semiconductor memory device may employ a duty cycle correction (DCC) circuit in order to adjust the duty cycle to 50%.
A known DCC circuit may have the limitations.
First, the known DCC circuits generate an up/down signal by comparing a width of high pulse and a width of low pulse of a clock and gradually correct a duty ratio according to the up/down signal. Such DCC circuits may complete the duty cycle correction after several comparison operations, and thus, the locking time may be long.
Second, digital type DCC circuits may have difficulty in measuring the duty ratio due to offsets of the duty detection circuits themselves.
Third, the duty cycle correction target, that is, the frequency range of the input clock, may be limited.